On-Chip Interconnect with aelite

Composable and Predictable Systems

Nonfiction, Science & Nature, Technology, Electronics, Circuits, Computers, Application Software, CAD/CAM
Cover of the book On-Chip Interconnect with aelite by Kees Goossens, Andreas Hansson, Springer New York
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Author: Kees Goossens, Andreas Hansson ISBN: 9781441968654
Publisher: Springer New York Publication: October 20, 2010
Imprint: Springer Language: English
Author: Kees Goossens, Andreas Hansson
ISBN: 9781441968654
Publisher: Springer New York
Publication: October 20, 2010
Imprint: Springer
Language: English

The book provides a comprehensive description and implementation methodology for the Philips/NXP Aethereal/aelite Network-on-Chip (NoC). The presentation offers a systems perspective, starting from the system requirements and deriving and describing the resulting hardware architectures, embedded software, and accompanying design flow. Readers get an in depth view of the interconnect requirements, not centered only on performance and scalability, but also the multi-faceted, application-driven requirements, in particular composability and predictability. The book shows how these qualitative requirements are implemented in a state-of-the-art on-chip interconnect, and presents the realistic, quantitative costs.

View on Amazon View on AbeBooks View on Kobo View on B.Depository View on eBay View on Walmart

The book provides a comprehensive description and implementation methodology for the Philips/NXP Aethereal/aelite Network-on-Chip (NoC). The presentation offers a systems perspective, starting from the system requirements and deriving and describing the resulting hardware architectures, embedded software, and accompanying design flow. Readers get an in depth view of the interconnect requirements, not centered only on performance and scalability, but also the multi-faceted, application-driven requirements, in particular composability and predictability. The book shows how these qualitative requirements are implemented in a state-of-the-art on-chip interconnect, and presents the realistic, quantitative costs.

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